The automotive industry is rapidly evolving undergoing a significant transformation in the manner that cars are being designed, manufactured, and operated. Most notably the safety of the automobile is highly influenced by the safety and reliability associated with semiconductor technologies. System integrators are challenged to build robust platforms that can reliably operate within the harsh automotive environment. Ensuring functional safety in this harsh environment is non-negotiable. And while compliance to automotive specifics is a given, compliance alone is not sufficient. As such, the integrator must leverage every available tool to guarantee it.
One tool for testing and available as a standard feature on GDDR6 SGRAM is Boundary Scan. Implemented at the IC level, Boundary Scan is an integrated method for testing interconnects at the board (PCB) level. In the past, PCB interconnect testing was done via a “bed of nails” which required physical contact with probe points on the board. Advances in silicon process, device packaging, and board mounting techniques have allowed for high density, minimum pitch interconnects. Physical contact with these types of interconnects for testing is difficult if not impossible.
The solution to the problem of testing high density interconnects was to create a scan path by designing in access to the device via internal registers. In 1988 the Joint Test Action Group (JTAG) was formed to standardize the design and protocol for Boundary Scan. The Boundary Scan elements are independent of the functionality of the device. Boundary Scan can confirm device presence, bonding, orientation, and interconnect integrity.
Why use Boundary Scan?
- It is standardized by IEEE 1149.1. This allows different vendors to design components for mix and match compatibility.
- Wide support by tool and test vendors.
- Allows much of the design and packaging analysis to be done prior to PCB layout.
- No need for expensive test fixtures.
- Integrates product development, production test, and device programming into one tool.
- Useful in fault isolation.
Micron automotive compliant GDDR6 SGRAM devices incorporate an IEEE 1149.1-2013 compliant test access port (TAP) in addition to the boundary scan cells found in each I/O. Each of the two channels on the device has its own TAP controller allowing for separate testability. Device temperature, which is also a critical aspect of automotive reliability, can be monitored via the TAP controller in parallel to mission mode operation with no resulting loss of performance.
The challenge of meeting functional safety requirements and associated memory bandwidth for the coming wave of autonomous vehicles is daunting. Leading to capabilities never imagined, Micron’s automotive compliant GDDR6 SGRAM is driving performance in automotive to new levels. In addition to performance, Micron has prioritized functionality that will aid designing and testing high reliability systems. Achieving functional safety is one of the many keys that are essential to unlocking the amazing future of automobiles.
Discover more about Micron's Automotive Solutions now.