DDR5 early collaboration with validation silicon enables the data currency of tomorrow

By Ryan Baxter - 2018-04-19

As systems feel the pressure of improving, the drive for increasing bandwidth for next generation memory is priority #1. DDR5 is being developed to deliver improved performance at double the bandwidth and density over DDR4. Specifically, it will double the transfers per second from DDR4 @ 3200MT/s to 6400MT/s for DDR5, while taking advantage of dual 32bit subchannels. This will enable more flexibility in parallel interface and improvement in efficiency leveraging the available bandwidth. Bringing DDR5 technology to market with these new features, is a difficult task and increasingly more difficult with process node shrinks and additional market demand pressure to do it faster than previous generations.

It has become critically important to develop the right and tight collaboration with partners and standards committees in order to execute and accelerate this process. Enabling the ecosystem to verify and test silicon, validate IP, secure best practices for firmware release for IO testing and operation. This is all hard work and in today's world must occur earlier in the design cycle and execute faster than ever before. In addition, memory companies like Micron, are developing system solutions that increase the complexity and features which push boundaries of system level testing that are new and very different to commodity memory devices.

In an effort to continue to enable the world with leading edge memory solutions, Micron is working directly with ecosystem partners in order to enable learning on both pre-silicon verification as well as validation. Micron has begun shipping early DDR5 validation silicon to our ecosystem partners. This early sampling of DDR5 will enable the engineering efforts to validate IP and to build robust models and toolsets in the ecosystem; IO settings for optimizing "data eyes"; board layout validation; validate IP assumptions; and more. This is the first of many critical steps a memory vendor should execute to validate assumptions with the ecosystem to support the next baseline memory in order to build broader based solutions prior to delivering samples to customers.

The key takeaway. Shipping early DDR5 validation silicon enables partners to validate IP, and tools and assumptions about the next great baseline of memory platforms for the broad market. This takes time and a collaborative partnership of companies, who work together very early in the product life cycle. Micron is proud to be in a position to contribute and partner in this fashion, in order to enable and feed the data currency of tomorrow.

Micron engaged with the ecosystem to enable DDR5 solutions
Micron engaged with the ecosystem to enable early DDR5 solutions.

Ryan Baxter

Ryan Baxter

Ryan Baxter is senior director of Cloud, Enterprise and Networking at Micron.