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The Bleeding Edge of Memory and Compute: Micron @ SC17

By Jay Walstrum - 2017-11-13
Categories Communities Company Events Executive Insight Corner Innovations Memory Storage
Products Advanced Computing Solutions Advanced Solutions DRAM DRAM Modules Managed NAND Memory Memory Cards Multichip Packages NAND Flash NOR Flash SpecTek SSDs Storage Storage Platforms Ultra-Bandwidth Solutions

SC17 will provide fresh solution ideas from Micron. It’s an exciting time in the industry for creative and collaborative memory developers and, teamed with the new leadership at Micron, this brings vibrant life to discussions and partnerships Micron will be talking about. Below are some highlights you will want to catch to stay ahead of the latest developments in memory and storage. Be sure to note these in your calendar.

Visit the Micron Booth

Talk with our memory experts in booth 1963 and check out the latest memory and storage solutions. Three key demos you don’t want to miss:

  • Deep Neural Networks complete with facial recognition training and inference operation. Micron Collaborates with Machine Learning experts to demonstrate solutions for deep Neural networks. These solutions are more efficient on power and break through the memory bandwidth wall.
  • Persistent Memory showcasing NVDIMMs in the latest Dell 14G Skylake platform.
  • Shared NMVe Storage a petabyte-scale unified pool of high-performance, low latency, NVMe flash storage distributed across multiple servers - yet it retains the speeds and latencies of directly-attached media.

And don’t miss these other chances to catch Micron at SC17: 

Memory Centric Architectures for Cloud and HPC

Hosted by Sudhakara Yalamanchili (Georgia Tech) & Peter Kogge (Uof Notre Dame); with Panelists: Steve Pawlowski (Micron); John Shalf (CTO of NERSC/DoE); Dave Mountain (LPS); Palo Faraboschi (HP Labs)
The goal of this BoF is to bring together application developers, system software developers, memory system designers, and system architects to create community that can identify major trends and technical challenges, and catalyze collaborative opportunities between industry, academia, and government to address them.
Birds of a Feather – Tues. Nov. 14, 5:15pm RM507

15th Graph500 List

Micron’s Rich Murphy will unveil the 15th Graph500 list, initial rankings for the new SSSP kernel released at ISC2017, and enhance the new energy metrics of the Green Graph500.
Birds of a Feather – Wed. Nov. 15, 12:15pm RM605

The Silver Lining of the Cloud is at the EDGE

Learn why the next big wave of Edge computing will be driven by the intelligent devices that proliferate across consumers, manufacturing, vehicles, households and remote installations. With Micron’s Revathi Narayana
Exhibitor Forum – Wed., Nov. 15, 1:30 RM501-502

Why Memory Matters in the New Data Economy

Micron Principal Solutions Architect, Brad Spiers, will be speaking at the Penguin Computing booth (1801) on how companies are looking to memory and storage-optimized solutions to handle the huge influx of data being generated.
In-Booth Lecture – Tues. Nov. 14, 5pm Booth 1801

This is an exciting time for memory solutions, so please stop by, reach out and find some time to chat with our Micron staff and executives.

Jay Walstrum

Jay Walstrum

Jay Walstrum is a Senior System Architect for Micron’s Compute and Networking Business Unit, where he is focusing on new opportunities in the three to five-plus year timeframe. In his role, he also applies innovative technologies and memory architectures to solve customer system-level challenges.

Jay’s responsibilities include working closely with a market-strategy team to identify new technology, applications, product/architecture specifications, customers, and markets for new product concepts. He also actively works with customer system architects, technologists, third-party developers, and Micron’s Research and Development team to identify, define, and architect innovative memory solutions.

Before beginning with Micron in January 2013, Jay spent 22 years at Xilinx Corp, where he held various positions ranging from the Director of Quality, to the Senior Product Planning Manager, to the Strategic and Technical Marketing Leader.

Jay holds a BSEE from University of Southern California. He holds 11 patents in the areas of FPGA system Solutions and memory interface architecture.

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